Energy and power: CMOS, DVFS, the end of Dennard and accelerators
Switching energy CV² proved, dynamic and static power, DVFS with power proportional to the cube of frequency, the energy argument for multicore, Dennard scaling and dark silicon, heterogeneous cores and accelerators.
For thirty years every generation of processors was faster than the previous one almost for free. Then, around 2005, the limit became heat: a chip cannot dissipate more than about a hundred watts per square centimetre without impractical cooling, and a phone no more than a few watts. Today every architectural choice is measured in performance per watt. In this lesson we prove where the dynamic power of CMOS circuits comes from, why lowering frequency and voltage saves so much, the end of Dennard scaling and the industry’s answers: multicore, heterogeneous cores and accelerators.
Dynamic power
Every node of a CMOS circuit has a capacitance 
(the gates it drives and the wires). When it goes from 0 to 1, the p transistor charges it from the supply 
; when it returns to 0, the n transistor discharges it to ground (Electronic Devices lesson on CMOS logic).
Theorem. A complete charge and discharge cycle of a capacitance at voltage dissipates the energy 
, whatever the resistance of the transistors.
Proof. During charging the supply delivers the charge 
at the constant voltage : the energy delivered is 
. At the end the capacitor stores 
; the other half, , has been dissipated in the transistor’s resistance, whatever its value (a large resistance gives a small current for a long time, and the product does not change). During discharge the stored energy is dissipated in the n transistor. In all, per cycle. ∎
If a node switches from 0 to 1 in a fraction 
of clock cycles (the activity factor), at frequency 
:
![\[ P_{dyn} = \alpha\,C\,V^2 f \]](https://www.electronics-engineering.com/wp-content/ql-cache/quicklatex.com-9a7fff78ff67da6486308d8d8a27fd4b_l3.png "Rendered by QuickLaTeX.com")
To this is added static power, due to the transistors’ leakage currents even when they are off, which grows rapidly as the threshold voltage is lowered and with temperature.
Frequency and voltage
A transistor switches faster if driven with a higher voltage: over a reasonable operating range, the maximum frequency is roughly proportional to the voltage. Dynamic voltage and frequency scaling (DVFS) lowers both together when maximum speed is not needed.
Theorem. If voltage is proportional to frequency, dynamic power is proportional to 
and energy per operation to 
.
Proof. With 
, 
. The number of operations per second is proportional to , so the energy per operation is 
, i.e. proportional to 
. ∎
The consequence for multicore. Lowering frequency and voltage by 20 %, a core’s power drops to 
of the initial value. Two cores slowed down in this way consume about as much as a single core at full frequency, but, if the work can be parallelised, they deliver 
times the performance. This is the energy argument that pushed towards multicore.
The end of Dennard scaling
In 1974 Robert Dennard showed that shrinking a transistor by a factor 
, voltages and capacitances drop by and frequency rises by : power per transistor drops by 
, exactly as much as the number of transistors in the same area grows. Power density stays constant, and every generation was faster without running hotter.
Around 2005 the rule broke: voltage can no longer drop, because transistor thresholds cannot drop without leakage currents exploding. Power density started to grow with every generation. The result is dark silicon: a modern chip has more logic than can be switched on all at once without exceeding the thermal limit.
The industry’s answers
- Multicore and frequencies stuck around 3-5 GHz, as the calculation above shows.
- Heterogeneous cores: big, fast cores for sequential parts, small efficient cores for background and parallel work (ARM’s big.LITTLE, Intel’s P and E cores). The operating system moves threads between them.
- Specialised accelerators: a circuit that does one thing only, such as video decoding, cryptography or neural network computation (NPU), can be 10 to 1000 times more efficient than a general-purpose processor, because it spends no energy fetching, decoding and reordering instructions. The “dark” silicon fills up with accelerators that switch on only when needed.
- Switching off what is idle: chip blocks with no clock (clock gating) or no supply (power gating) when inactive; it often pays to run a job at full speed and then switch everything off (race to idle) rather than run it slowly.
A last lesson from the numbers: moving data costs more than computing on it. A 64-bit floating-point addition costs a few picojoules; reading its operands from DRAM costs a hundred times more. The same techniques that improve performance, data locality, blocking, high arithmetic intensity, are those that save energy.
