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Digital Signal Processing

Digital filter structures: biquads, fixed point and round-off noise

Direct and transposed forms, pole sensitivity to coefficients with proof, cascade of second-order sections, fixed point and overflow, round-off noise proved, limit cycles, DSP architecture.

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Once the coefficients are computed, the filter must be implemented: in a DSP, a microcontroller, an FPGA. Mathematically all structures are equivalent, but with finite-precision numbers they behave very differently. In this lesson we look at the direct forms and the second-order section, the sensitivity of poles to coefficients with its proof, fixed-point arithmetic, round-off noise with the proof of its power formula, and limit cycles.

The direct forms

An IIR filter H(z) = B(z)/A(z) corresponds to the difference equation

    \[ y[n] = \sum_{k=0}^{M} b_k\,x[n-k] - \sum_{k=1}^{N} a_k\,y[n-k] \]

Direct form I implements it as it stands, with two delay lines, one for inputs and one for outputs. Direct form II swaps the order of the two parts (the system is linear, order does not matter) and shares a single delay line: it uses the minimum number of memory cells, \max(M, N). The transposed form is obtained by reversing the direction of all branches and swapping input and output: it has the same transfer function and better numerical behaviour, because the additions happen right after the multiplications.

Second-order section in transposed direct form II
The input multiplied by b_0, b_1 and b_2 enters three summing nodes linked by two delays; the output, multiplied by minus a_1 and minus a_2, returns to the lower nodes. Two memory cells are enough for the whole second-order filter.

Why second-order sections are used

A high-order IIR filter implemented in direct form, with a single polynomial in the denominator, is dangerous: small errors in the coefficients move the poles a lot.

Theorem. Let A(z) = \prod_{j=1}^{N}(1 - p_jz^{-1}) with distinct poles. The sensitivity of pole p_i to coefficient a_k is

    \[ \frac{\partial p_i}{\partial a_k} = -\frac{p_i^{\,N-k}}{\prod_{j\ne i}(p_i - p_j)} \]

Proof. Write the denominator as a polynomial in z: P(z) = z^N A(z) = z^N + a_1z^{N-1} + \dots + a_N, with roots p_j. For every pole P(p_i) = 0. Differentiating with respect to a_k, taking into account that p_i depends on a_k:

    \[ P'(p_i)\,\frac{\partial p_i}{\partial a_k} + p_i^{\,N-k} = 0 \]

because \partial P/\partial a_k = z^{N-k}. Finally P(z) = \prod(z - p_j) gives P'(p_i) = \prod_{j\ne i}(p_i - p_j). ∎

The denominator is the product of the distances between the pole and all the others: if the poles are close together, as happens in selective filters, where they crowd near the unit circle around the passband, the sensitivity blows up. A rounding error on the coefficients can move a pole outside the circle and make the filter unstable. That is why an IIR filter is factored into a cascade of second-order sections (biquads), each with a single pair of poles: sensitivities stay small, each section can be checked on its own, and the order of the sections and the distribution of gain are chosen to reduce noise.

Fixed point

In inexpensive DSPs and in dedicated hardware numbers are in fixed point: for instance in Q15 format a 16-bit integer represents a value between -1 and 1 - 2^{-15}. There are two problems:

  • overflow: a sum exceeding 1 wraps around to -1, with an enormous error. It is prevented by scaling the signal at the input of each section, so that internal nodes do not exceed full scale, and the damage is limited by saturation arithmetic, which clamps the result at the maximum instead of letting it wrap;
  • quantisation: every product has twice the bits and must be rounded, introducing a small error at every step. DSPs accumulate sums in longer registers (40 bits or more) and round only once at the end.

Round-off noise

The rounding error with step q is modelled as white noise uniform between -q/2 and q/2, with power q^2/12 (Signal Theory lesson on quantisation). But this noise does not leave the filter as it is: it goes through the part of the filter between the point where it arises and the output.

Theorem. White noise of power \sigma^2 entering a system with impulse response h_e[n] produces at the output noise of power

    \[ \sigma_y^2 = \sigma^2\sum_{n=0}^{\infty}h_e^2[n] \]

Proof. The output is y[n] = \sum_k h_e[k]e[n-k]. Its power is E[y^2] = \sum_k\sum_l h_e[k]h_e[l]\,E[e[n-k]e[n-l]]. For white noise E[e[n-k]e[n-l]] = \sigma^2 if k = l and 0 otherwise, so only the sum of the terms with k = l remains. ∎

Example. A first-order section y[n] = a\,y[n-1] + x[n], with rounding at the summing node: the noise sees the whole filter, h_e[n] = a^n, and \sum a^{2n} = 1/(1 - a^2). With a = 0.99, a pole close to the circle, the factor is about 50, i.e. 17 dB more noise than a single rounding: almost 3 bits lost. This is why very selective low-frequency filters, with poles near z = 1, need more bits.

Limit cycles

In fixed-point IIR filters it can happen that, with zero input, the output does not go to zero but stays stuck at a constant value or a small oscillation: a limit cycle. Rounding causes it, by making the system non-linear: for instance with y[n] = \mathrm{round}(0.9\,y[n-1]), starting from 4 one gets 3.6 \to 4, and the output stays at 4 forever instead of decaying. Limit cycles are avoided by rounding towards zero (magnitude truncation) or with special structures; in audio filters they are heard as faint tones in silence. FIR filters have no feedback, so they have neither limit cycles nor stability problems: another reason to choose them when precision is scarce.

DSP architecture

Signal processors are built around the operation \text{accumulator} \mathrel{+}= a\cdot b: a multiply-accumulate unit (MAC) that performs a product and a sum in one cycle, separate memories for data and coefficients read in parallel, circular buffers handled in hardware for delay lines and zero-overhead loops. An N-tap FIR filter thus costs about N cycles per sample. Today the same principles are found in the SIMD instructions of general-purpose processors and in the DSP blocks of FPGAs.

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