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Microelectronics

Interconnects: wire delay, repeaters, crosstalk and electromigration

Wire resistance and capacitance, delay quadratic in length proved, repeaters that make it linear proved, crosstalk and the Miller effect, supply drop, electromigration.

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In the first integrated circuits interconnects were “free”: all the delay was in the transistors. With scaling, transistors became faster while wires became thinner and more resistive, and today in a large chip delay, power and most design problems lie in the interconnects. In this lesson we look at the resistance and capacitance of wires, the proof that the delay of a wire grows with the square of its length, repeaters with the proof that they make delay linear, crosstalk, supply drops and electromigration.

Resistance and capacitance of a wire

A copper wire of length L, width W and thickness t has resistance

    \[ R = \rho\frac{L}{Wt} \]

In the lowest levels wires have cross-sections a few tens of nanometres on a side, and copper’s effective resistivity rises above its bulk value because electrons scatter off the surfaces and grain boundaries; moreover part of the cross-section is taken by the barrier that prevents copper from diffusing. A minimum wire can have hundreds of ohms per micrometre. The capacitance to neighbouring wires and to the layers above and below is about 0.1-0.2 fF per micrometre, almost independent of dimensions because width and spacings scale together.

The delay of a long wire

A wire is a distributed RC network: each segment has its own resistance and capacitance.

Theorem. The delay of a wire not driven by repeaters grows with the square of its length.

Proof. With resistance r and capacitance c per unit length, divide the wire into N segments, each with resistance rL/N and capacitance cL/N. By the Elmore delay (lesson on delays), the capacitance of segment k is charged through k resistances: t_D = \sum_{k=1}^{N}\frac{cL}{N}\cdot\frac{k\,rL}{N} = rcL^2\frac{N(N+1)}{2N^2}, which for large N tends to \frac{1}{2}rcL^2. In any case the delay is proportional to L^2, because doubling the length doubles both the resistance and the capacitance. ∎

The more precise 50 % delay of a distributed line is 0.38\,rcL^2. A 1 mm wire with 100 Ω/µm and 0.2 fF/µm has rcL^2 = 20 ns: unacceptable in a processor working with 250 ps cycles.

Repeaters

The solution is to break the wire into k segments, each driven by a repeater (an inverter or a buffer).

Theorem. With an optimal number of repeaters the delay of a wire becomes proportional to its length.

Proof. Each segment has length L/k and delay t_b + a\,rc(L/k)^2, where t_b is the repeater delay and a a constant. The total is D(k) = k\,t_b + a\,rcL^2/k. Differentiating with respect to k and setting it to zero: t_b = a\,rcL^2/k^2, i.e. k_{opt} = L\sqrt{a\,rc/t_b}. Substituting, the two terms are equal and D_{min} = 2L\sqrt{a\,rc\,t_b}: proportional to L. ∎

Delay of an interconnect as a function of length
Without repeaters the delay grows with the square of the length (red); with the optimal number of repeaters it grows linearly (green). Beyond a certain length repeaters are indispensable.

Modern processors contain millions of repeaters, which consume area and power. Long interconnects are routed in the upper metal levels, thicker and wider, with much lower resistance; and architectures are organised so that global signals are few, with data processed locally (Computer Architecture lesson on caches).

Crosstalk

Two close parallel wires form a capacitor: when one switches, it injects a disturbance into the other through the coupling capacitance, which in the lower levels is the largest part of the total capacitance. Two effects arise:

  • noise on a quiet wire, which can exceed a gate’s threshold and cause an error;
  • delay variations: if the neighbour switches in the opposite direction, the coupling capacitance sees twice the voltage change and it is as if it doubled (Miller effect); if it switches in the same direction, it is as if it vanished. The delay of a wire therefore depends on what its neighbours do, and timing analysis (lesson on the design flow) must take this into account.

It is fought by spacing critical wires, shielding them with ground wires, and alternating wire directions between one level and the next.

Supply and electromigration

The power network is also made of resistive wires: tens of amperes flowing through it produce voltage drops (IR drop), and rapidly changing currents produce inductive drops (L\,di/dt) in the package. If the supply drops locally by 10 %, transistors slow down and timing no longer closes. Dense power grids, thousands of contacts with the package and on-chip decoupling capacitors are used.

Electromigration is the movement of metal atoms dragged by the flow of electrons at high current density: over the years voids form that break the wire and hillocks that short it to its neighbour. The mean lifetime follows Black’s law, inversely proportional to a power of the current density and decreasing exponentially with temperature. Design rules set the maximum current density in every wire.

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