Wired data transmission: termination, eye, equalisation and line codes

Not all telecommunications go through the air: between one board and another, between a computer and a peripheral, between two units in a rack, data travel on cables and traces at speeds from a few kilobits to tens of gigabits per second. The electronics that transmits them must handle reflections, attenuation, noise and clock recovery. In this lesson we look at the classic serial interfaces, line termination with the criterion for when it is needed and an example, differential transmission, the eye diagram, equalisation, and line codes with the proof of zero DC content.

The classic serial interfaces

• RS-232: a single ground-referenced line per direction, with levels of ±3-15 V; a few metres and a few hundred kbit/s. Simple, still widespread for configuring equipment; it has numerous control signals and 9 or 25-pin connectors.
• RS-422 and RS-485: differential transmission on a twisted pair, up to 1200 m or 10 Mbit/s (not both together); RS-485 allows several transmitters on the same bus, and is the basis of many fieldbuses such as Modbus RTU and PROFIBUS (Automation Systems Design lesson on industrial networks).

When a line is long

A connection behaves like a transmission line (Electromagnetic Fields lesson on transmission lines) when the signal’s round-trip time is comparable with its rise time: then reflections from the far end return while the edge is still rising, and the signal is distorted with steps and ringing. If the rise time is and the line’s propagation delay is , the rule of thumb is: the line must be terminated if (roughly).

At the end terminated in the reflection coefficient is (lesson on S-parameters): a termination equal to the characteristic impedance cancels the reflection.

Example. RS-485 at 10 Mbit/s: a bit lasts 100 ns and the edges about 10-20 ns. On a cable with 5 ns/m delay, as little as 2 m gives 20 ns round trip: the line must be terminated with 120 Ω (the typical twisted-pair impedance) at both ends, because the bus is traversed in both directions. At 9600 bit/s, with slow edges, a bus of a few tens of metres would work even without; terminations are needed anyway beyond certain lengths, and bias resistors guarantee a defined state when nobody is transmitting.

Differential transmission

A differential signal travels on two conductors with opposite voltages, and the receiver looks at the difference. Disturbances induced equally on both (common mode) cancel; equal and opposite currents produce fields that cancel at a distance, so the pair radiates little (Electromagnetic Compatibility lesson on radiated emissions). This is why all fast interfaces are differential: LVDS, USB, Ethernet, HDMI, PCI Express, SATA. With swings of a few hundred millivolts they consume little and switch fast.

The eye diagram

Overlaying on the oscilloscope all the bit intervals of a received signal, synchronised with the clock, gives the eye diagram.

The vertical opening is the margin against noise and intersymbol interference; the horizontal opening is the interval in which sampling can take place, reduced by jitter. A closed eye means errors. Fast interface standards specify a mask: a central zone that no trace may enter.

Equalisation

Real lines attenuate high frequencies more: the skin effect makes resistance grow with the square root of frequency, dielectric losses with frequency. At many gigabits per second a 30 cm PCB trace can attenuate by 20-30 dB at half the bit rate, and bits smear into their neighbours (intersymbol interference), closing the eye. Fast serial transceivers (SerDes) compensate with equalisation:

• at the transmitter, edge emphasis: the first bit after a transition is transmitted with larger amplitude;
• at the receiver, a filter boosting high frequencies (CTLE) and a decision feedback equaliser (DFE), which subtracts the effect of already decided bits from the current bit;
• all adaptive: the coefficients adjust themselves at link start-up (Digital Signal Processing lesson on adaptive filters).

The clock is not transmitted: the receiver reconstructs it from the data transitions with a phase-locked loop (clock recovery). Enough transitions are therefore needed.

Line codes

Long runs of zeros or ones have no transitions and shift the signal’s average value, which coupling capacitors between boards do not pass. Line codes solve this:

Theorem. Manchester coding, which represents each bit with a transition in the middle of the bit (high-low for 1, low-high for 0, or vice versa), produces a signal with zero average over every bit and at least one transition per bit.

Proof. Each bit occupies two equal half intervals, one at level and one at , in one order or the other: the average over each bit is , whatever the sequence, and the change in the middle of the bit is a guaranteed transition. ∎

The price is doubling the bandwidth. Block codes are more efficient: 8b/10b maps 8 bits into 10-bit words chosen so that the accumulated difference between ones and zeros (the “running disparity”) stays bounded, with 25 % overhead; 64b/66b and 128b/130b use a scrambler that makes the sequence almost random and a short synchronisation header, with overheads of 3 % and 1.5 %. Example. PCI Express 3.0 transmits at 8 GT/s per lane with 128b/130b coding: Gbit/s of payload; version 2.0, at 5 GT/s with 8b/10b, gave 4. The most recent versions use four-level modulation (PAM4), which carries two bits per symbol at the price of an eye three times smaller, and forward error correction.